列挙体定義書 - pci_dev_reg

enum pci_dev_reg_5

No.	名称	属性	説明
1	pci_dev_reg_5
	P_CTL_DIV_CORE_CLK_ENA	1<<31	Divide Core Clock Enable
	P_CTL_SRESET_VMAIN_AV	1<<30	Soft Reset for Vmain_av De-Glitch
	P_CTL_BYPASS_VMAIN_AV	1<<29	Bypass En. for Vmain_av De-Glitch
	P_CTL_TIM_VMAIN_AV_MSK	3<<27	Bit 28..27: Timer Vmain_av Mask
	P_REL_PCIE_RST_DE_ASS	1<<26	PCIe Reset De-Asserted
	P_REL_GPHY_REC_PACKET	1<<25	GPHY Received Packet
	P_REL_INT_FIFO_N_EMPTY	1<<24	Internal FIFO Not Empty
	P_REL_MAIN_PWR_AVAIL	1<<23	Main Power Available
	P_REL_CLKRUN_REQ_REL	1<<22	CLKRUN Request Release
	P_REL_PCIE_RESET_ASS	1<<21	PCIe Reset Asserted
	P_REL_PME_ASSERTED	1<<20	PME Asserted
	P_REL_PCIE_EXIT_L1_ST	1<<19	PCIe Exit L1 State
	P_REL_LOADER_NOT_FIN	1<<18	EPROM Loader Not Finished
	P_REL_PCIE_RX_EX_IDLE	1<<17	PCIe Rx Exit Electrical Idle State
	P_REL_GPHY_LINK_UP	1<<16	GPHY Link Up
	P_GAT_PCIE_RST_ASSERTED	1<<10	PCIe Reset Asserted
	P_GAT_GPHY_N_REC_PACKET	1<<9	GPHY Not Received Packet
	P_GAT_INT_FIFO_EMPTY	1<<8	Internal FIFO Empty
	P_GAT_MAIN_PWR_N_AVAIL	1<<7	Main Power Not Available
	P_GAT_CLKRUN_REQ_REL	1<<6	CLKRUN Not Requested
	P_GAT_PCIE_RESET_ASS	1<<5	PCIe Reset Asserted
	P_GAT_PME_DE_ASSERTED	1<<4	PME De-Asserted
	P_GAT_PCIE_ENTER_L1_ST	1<<3	PCIe Enter L1 State
	P_GAT_LOADER_FINISHED	1<<2	EPROM Loader Finished
	P_GAT_PCIE_RX_EL_IDLE	1<<1	PCIe Rx Electrical Idle State
	P_GAT_GPHY_LINK_DOWN	1<<0	GPHY Link Down
	PCIE_OUR5_EVENT_CLK_D3_SET	P_REL_GPHY_REC_PACKET \| P_REL_INT_FIFO_N_EMPTY \| P_REL_PCIE_EXIT_L1_ST \| P_REL_PCIE_RX_EX_IDLE \| P

pci_dev_reg_5