enum epic100_registers
No. | 名称 | 属性 | 説明 |
---|---|---|---|
1 |
epic100_registers | ||
COMMAND | 0 | Control Register | |
INTSTAT | 4 | Interrupt Status | |
INTMASK | 8 | Interrupt Mask | |
GENCTL | 0x0C | General Control | |
NVCTL | 0x10 | Non Volatile Control | |
EECTL | 0x14 | EEPROM Control | |
TEST | 0x1C | Test register: marked as reserved (see in source code) | |
CRCCNT | 0x20 | CRC Error Counter | |
ALICNT | 0x24 | Frame Alignment Error Counter | |
MPCNT | 0x28 | Missed Packet Counter | |
MMCTL | 0x30 | MII Management Interface Control | |
MMDATA | 0x34 | MII Management Interface Data | |
MIICFG | 0x38 | MII Configuration | |
IPG | 0x3C | InterPacket Gap | |
LAN0 | 0x40 | MAC address. (0x40-0x48) | |
IDCHK | 0x4C | BoardID/ Checksum | |
MC0 | 0x50 | Multicast filter table. (0x50-0x5c) | |
RXCON | 0x60 | Receive Control | |
TXCON | 0x70 | Transmit Control | |
TXSTAT | 0x74 | Transmit Status | |
PRCDAR | 0x84 | PCI Receive Current Descriptor Address | |
PRSTAT | 0xA4 | PCI Receive DMA Status | |
PRCPTHR | 0xB0 | PCI Receive Copy Threshold | |
PTCDAR | 0xC4 | PCI Transmit Current Descriptor Address | |
ETHTHR | 0xDC | Early Transmit Threshold |
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